1. Field of the Invention
The present invention relates to semiconductor memory devices such as dynamic random-access memories (DRAM), which are designed to cancel out characteristic dispersions of single-ended sense amplifiers each including a single metal-oxide semiconductor (MOS) transistor due to dispersions of threshold voltages of MOS transistors in manufacturing processes and due to temperature dependency thereof.
The present application claims priority on Japanese Patent Application No. 2008-98246, the content of which is incorporated herein by reference.
2. Description of Related Art
Conventionally, semiconductor memory devices having sense amplifiers compensating for characteristic dispersions due to temperature variations have been developed and disclosed in various documents such as Patent Documents 1-9.                Patent Document 1: Japanese Unexamined Patent Application Publication No. S58-168310        Patent Document 2: Japanese Unexamined Patent Application Publication No. S60-157797        Patent Document 3: Japanese Unexamined Patent Application Publication No. S62-42397        Patent Document 4: Japanese Unexamined Patent Application Publication No. 2004-273110        Patent Document 5: Japanese Unexamined Patent Application Publication No. 2005-182873        Patent Document 6: Japanese Unexamined Patent Application Publication No. 2006-172683        Patent Document 7: Japanese Unexamined Patent Application Publication No. H06-243678        Patent Document 8: Japanese Unexamined Patent Application Publication No. H06-203587        Patent Document 9: Japanese Patent Application Publication No.        
Patent Document 1 teaches a sense amplifier which varies a reference signal level of a differential amplifier circuit based on temperature so as to stabilize an output signal of the differential amplifier circuit. This technology aims at adjusting the gain of the differential amplifier circuit and is not applicable to a single-ended sense amplifier including a single MOS transistor.
Patent Document 2 teaches a temperature-compensation bubble memory system, in which a temperature compensation circuit forms a temperature-compensated reference voltage based on an output signal of a temperature sensor so that a sense amplifier generates a logic level based on a threshold level corresponding to the reference voltage. Patent Document 2 fails to teach the specific circuit configuration regarding the temperature sensor, temperature compensation circuit, and the sense amplifier; hence, it is not applicable to a single-ended sense amplifier including a single MOS transistor.
Patent Document 3 teaches a temperature-compensation type sense amplifier in which a plurality of temperature-compensating parts is used to cancel out temperature variations regarding the resistance, β gain, and parasitic capacitance. This technology is preferably applicable to a bipolar sense amplifier but is not applicable to a single-ended sense amplifier including a single MOS transistor.
Patent Document 4 teaches a temperature-compensation PRAM sense amplifier compensating for temperature variations of the resistance of a memory resistor. This technology is designed to compensate for the temperature dependency of the memory resistor but is not designed to compensate for the temperature dependency of the sense amplifier; hence, it is not applicable to a single-ended sense amplifier including a single MOS transistor.
Patent Document 5 teaches a semiconductor memory device for improving sense margins. This technology is designed to shift a cell-plate voltage by a certain value based on write date at a write time, thus increasing accumulated charges. Patent Document 6 teaches a semiconductor device which is designed to prevent dispersions of write voltage due to dispersions of threshold voltages of transistors for selecting cells in a full write operation that is performed using a cell-plate voltage without boosting a word-line voltage.
Patent Document 7 teaches a dynamic RAM with its plate-voltage setting method and information processing system, in which a cell-plate voltage is controlled to set the same leak current for a capacitor of a DRAM cell in both high and low levels. However, these technologies are incapable of compensating for threshold-voltage variations of a single-ended sense amplifier.
Patent Document 8 teaches a sense amplifier with its data-line load circuit, level shifter, and amplification circuit, which are designed to stabilize the operation of a single-ended sense amplifier adapted to a memory. Patent Document 9 teaches a low-voltage dynamic memory, which is designed to narrow down the amplitude of a bit-line voltage of a memory cell to its median, thus reducing the leak current of a transistor for selecting a cell. Both technologies are incapable of compensating for threshold-voltage variations of a single-ended sense amplifier.
The present inventors have recognized that conventionally-known sense amplifiers compensating for characteristic variations due to temperature variations and conventionally-known technologies for improving sense margins are incapable of compensating for threshold-voltage variations of single-ended sense amplifiers.
The present invention is made in consideration of the above circumstances so as to provide a semiconductor memory device which is capable of canceling out characteristic dispersions of single-ended sense amplifiers due to dispersions of threshold voltages of MOS transistors in manufacturing processes and due to temperature dependency thereof.